1. Field of the invention
This invention generally relates to a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a method for manufacturing it. In particular, this invention relates to a MOSFET with a fully overlapped LDD (Lightly Doped Drain) structure and a method for manufacturing it, which allows the MOSFET to be made smaller than is possible by conventional manufacturing techniques while providing improved performance.
2. Description of the prior art
As the dimensions of integrated circuits are scaled down into the submicron range, the reliability of MOSFET devices is increasingly affected by the electron effect or punchthrough effect, which are important problems that must be solved. Accordingly, a MOSFET with an LDD structure is disclosed. A conventional manufacturing method for the MOSFET comprises the following steps:
(1) Referring to FIG. 1a, a gate oxide 100 and a polysilicon layer 102 are sequentially formed on a substrate 1, and being defined on a channel region of the MOSFET to form a gate 10 thereof. PA1 (2) Referring to FIG. 1b, a dopant such as arsenic is doped into the substrate 1 by using the gate 10 as a mask to form lightly doped regions 12a and 12b. PA1 (3) As shown in FIG. 1c, sidewall spacers 120a and 120b are formed on the sidewalls of the gate 10. For instance, an oxide layer is first deposited thereon, and which is then etched back in a plasma etching step to form the spacers 120a and 120b. PA1 (4) Referring to FIG. 1d, a dopant is doped into the substrate 1. Heavily doped regions 14a and 14b are thereby formed under the sidewall spacers 120a, 120b and the gate 10. The heavily doped regions 14a and 14b in combination with the remaining lightly doped regions 12a and 12b respectively form the drain and the source of the MOSFET.
However, as the dimensions of the MOSFET devices are scaled down, the channel region of the MOSFET between the drain and the source is also shortened. Furthermore, the ratio of the lightly doped region to the channel region becomes greater. This causes a deterioration of the performance of the MOSFET because the resistance of the lightly doped region is larger than that of the heavily doped region. In addition, the punchthrough effect caused by the scaled-down dimensions deters the normal operation of the MOSFET device.